The use in computer systems of relatively small, high speed cache memories in conjunction with large, relatively slow main memories is well known as explained in "Computer Engineering--A DEC View of Hardware System Design", Chapter 10, pages 263-267, entitled "Cache Memories for PDP-11 Family Computers" by William D. Strecker. Such cache memories act as a buffer between the main memory and a central processor (CPU). Thus, the CPU fetches information (i.e., instructions and data) through the cache rather than directly from the main memory in order to reduce execution time in the overall system.
Normally, in a system which uses a store-to type cache, whenever the address in the cache is not the same as the address in the main memory to which the CPU wants to write (i.e., a "miss") and the data presently stored in the cache location has previously been changed from the data stored in the corresponding location in main memory (i.e., the cache is "dirty") the cache must always write its data back to the main memory before doing a read of new data from the main memory. Unfortunately, main memory accesses are relatively slow since the main memory address must have time to settle before an access can begin and the time required before valid data appears at the outputs of of the random access memories (RAMs) used in the main memory after a valid address is present at the main memory address inputs is quite long. Therefore, main memory accesses hold up the operation of the entire computer system.
Thus, the time penalty for a clean cache miss is one main memory read access, and the time penalty for a dirty cache miss, unfortunately, is two main memory accesses: one to write back the old data and one to read in the new data. If the effective time penalty for a dirty cache miss could be reduced to only one main memory access, overall system performance would be significantly improved.